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HANBit
HSD64M72D18RP
Synchronous DRAM Module 512Mbyte (64Mx72bit), DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V GENERAL DESCRIPTION
The HSD64M72D18RP is a 64M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 64M x 4 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD64M72D18RP is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
Part No. HSD64M72D18RP
FEATURES
* Part Identification HSD64M72D18RP-10L : 100MHz (CL=3) HSD64M72D18RP-10 : 100MHz (CL=2) HSD64M72D18RP-13 : 133MHz (CL=3)
* Burst mode operation * Auto & self refresh capability (8192 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system cloc * serial presence detect with EEPROM * The used device is 16M x 4bit x 4Banks SDRAM
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PIN ASSIGNMENT
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol Vss DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VCC NC NC VCC /WE DQM0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol DQM1 /CS0 NC Vss A0 A2 A4 A6 A8 A10 BA1 VCC VCC CLK0 Vss NC /CS2 DQM2 DQM3 NC VCC NC NC CB2 CB3 Vss DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol DQ18 DQ19 VDD DQ20 NC NC(*VREF) *CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 Vss *CLK2 NC WP **SDA **SCL VCC PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Symbol Vss DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 Vss NC NC VCC /CAS DQM4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
HSD64M72D18RP
Symbol DQM5 */CS1 /RAS Vss A1 A3 A5 A7 A9 BA0 A11 VCC *CLK1 A12 Vss CKE0 */CS3 DQM6 DQM7 *A13 VCC NC NC CB6 CB7 Vss DQ48 DQ49
PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Symbol DQ50 DQ51 VCC DQ52 NC NC(*VREF) REGE Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 Vss *CLK3 NC **SA0 **SA1 **SA2 VCC
* These pins are not used in this module *Pin Names A0~A12: Address input (Multiplexed) DQ0~DQ63: Data input/output CLK0~CLK3: Clock input /CS0~/CS3: Chip select input /CAS: Coulmn address strobe DQM0~7: DQM VSS: Ground REGE: Register enable SCL: Serial clock WP: Write protection NC: No connection
** These pins should be NC in the system which does not support SPD BA0~BA1: Select bank CB0~7: Check bit (Data-in/data-out) CKE0~ CKE1: Clock enable input /RAS: Row address strobe /WE: Write enable VCC: Power supply(3.3V) *VREF:Power supply for reference SDA: Serial data I/O SA0~2: Address in EEPROM
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FUNCTIONAL BLOCK DIAGRAM
HSD64M72D18RP
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PIN FUNCTION DESCRIPTION
Pin CLK /CS Name System clock Chip select Input Function
HSD64M72D18RP
Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9,CA11
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge.
/CAS
Column strobe
address
Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access.
/WE
Write
enable
Enables write operation and row precharge. Latches data in starting from /CAS, /WE active.
DQM0 ~ 7
Data mask
input/output
Makes data output Hi-Z, tsHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. The inputs are strobed in the latch/flip-flop on the riging edge of CLK. REGE is tied to VDD through 10K ohm register on PCB. So if REGE of module is floating, this module will be operated as registerd mode.
REGE
Register enable
DQ0 ~ 63 CB0~7 WP
Data input/output Check bit Write Protection
Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. WP pin is connected to Vcc. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected.
Vcc /VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
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ABSOLUTE MAXIMUM RATINGS
HSD64M72D18RP
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature
SYMBOL VIN ,OUT Vcc PD TSTG
RATING -1V to 4.6V -1V to 4.6V 18W -55oC to 150oC
Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 UNIT V V V V V 1 2 IOH = -2mA IOL = 2mA 3 NOTE
Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCC. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(Vcc = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV)
DESCRIPTION Input capacitance(A0~A12) Input capacitance(/RAS, /CAS,/WE) Input capacitance(CKE0) Input capacitance(CLK0) Input capacitance(/CS0~/CS3) Input capacitance(DQM0~DQM7) Input capacitance(BA0~BA1) Data input/output capacitance (DQ0 ~ DQ63) Data input/output capacitance (CB0 ~ CB7)
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SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 CIN3 CIN3 COUT COUT1
MIN
MAX 15 15 20 15 15 15 15 16 16
UNITS pF pF pF pF pF pF pF pF pF
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DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current (One bank active) Precharge standby current in power-down mode ICC2PS ICC1 tRC tRC(min) IO = 0mA ICC2P CKE VIL(max), tCC=10ns CKE & CLK VIL(max), tCC= CKE VIH(min) ICC2N /CS VIH(min), tcc=10ns 638 368 38 2,660 -13 -10
HSD64M72D18RP
VERSION UNIT -10L
NOT E
2,480
2,480
mA
1,3
mA mA
3 3
Precharge standby current in non power-down mode
Input signals are changed one time during 20ns CKE VIH(min) mA 3
ICC2NS
CLK VIL(max),
tcc=
254
Input signals are stable Active standby current in power-down mode ICC3P ICC3PS CKE VIL(max), tcc=10ns CKE&CLK VIL(max) tcc= CKEVIH(min), ICC3N /CSVIH(min), tcc=10ns 890 mA 3 458 mA 110 3
Active standby current in non power-down mode (One bank active)
Input signals are changed one time during 20ns CKEVIH(min)
ICC3NS
CLK VIL(max),
tcc=
452
Input signals are stable IO = 0 mA Operating current (Burst mode) ICC4 Page burst 3,020 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC tRC(min) 4,460 4,280 404 4,280 mA mA 2,3 3 2,570 2,570 mA 1,3
Self refresh current ICC6 CKE 0.2V Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1PLL & 2 Drive Ics. 4. Unless otherwise noticed, input swing level is CMOS(V IH/VIL= VCCQ/VSSQ).
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AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
HSD64M72D18RP
UNIT V V ns V
+3.3V
1200 DOUT 870 50pF*
Vtt=1.4V
50 VOH (DC) = 2.4V, IOH = -2mA DOUT VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load Z0=50 50pF
vss
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay /RAS to /CAS delay Row precharge time Row active time SYMBOL -13 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 Number of valid output data URL:www.hbe.co.kr REV.1.0 (August.2002)
UNIT -10 20 20 20 50 100 65 70 2 2CLK + 20ns 1 1 1 2 ea 1 70 -10L 20 20 20 50 ns ns ns ns ns ns CLK CLK CLK CLK 15 20 20 45
NOTE 1 1 1 1
Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay
1 2,5 5 2 2 3 4
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HSD64M72D18RP
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -13 PARAMETER CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 tCC CAS latency=2 CAS latency=3 tSAC CAS latency=2 CAS latency=3 tOH CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ CAS latency=2 6 7 ns 1 2.5 2.5 1.5 0.8 1 5.4 3 3 3 2 1 1 6 3 3 3 2 1 1 6 ns ns ns ns ns ns 3 3 3 3 2 1 3 3 6 3 ns 1,2 7 5.4 SYMBOL MIN 7.5 1000 10 6 MAX MIN 10 1000 12 6 ns 1,2 MAX MIN 10 1000 ns 1 MAX -10 -10L UNIT NOTE
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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SIMPLIFIED TRUTH TABLE
CK E n-1 H H L H CKE n X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1
HSD64M72D18RP
COMMAND Register Mode register set Auto refresh Refresh Self refres h Read & column addres s Write & column addres s Precharg e Auto disable Auto precharge eable Auto disable Auto enable precharge precharge Entry Exit
A10/ AP OP code X X
A11 A9~A0
NOTE 1,2 3 3 3 3
Bank active & row addr. precharge
Row address L Column Address (A0 ~ A9),A11 Column Address (A0 A9),A11 X ~ 4 4,5 4 4,5 6 X
H
X
L
H
L
H
X
V H L
H
X
L
H
L
L
X
V H
Burst Stop Bank selection All banks Entry Exit Entry Exit
H H H L H L H H
X X L H L H
L L H L X H L H L H L
H L X V X X H X V X X H
H H X V X X H X V X H
L L X V X X H X V X H
X X X X X V X L H
Clock suspend or active power down
X
Precharge down mode DQM
power
X X V X X X 7
No operation command
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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TIMING DIAGRAMS
HSD64M72D18RP
td, tr = Delay of register (74LVC162835) Notes : 1.In case of module timing, command cycles 1CLK with respect to external input timing at the address and input signal because of the buffering in register (74LVC162835). Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered DIMMs. 2. DIN is to be issued 1 clock after write command in external timing because D IN is issued directly to module.
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HSD64M72D18RP
PACKAGING INFORMATION
Unit : inch [mm] Front - Side TOLERANCE : 0.008 [ 0.20 ]
ORDERING INFORMATION
Part Number
Density
Org.
Package 168 Pin-DIMM /Low Profile 168 Pin-DIMM /Low Profile 168 Pin-DIMM /Low Profile
Ref.
Vcc
MODE Registered /ECC Registered /ECC Registered /ECC
MAX.frq 100MHz CL=2 100MHz CL=3 133MHz CL=3
HSD64M72D18RP-10 HSD64M72D18RP-10L HSD64M72D18RP-13
512MByte 512MByte 512MByte
64M x 72 64M x 72 64M x 72
8K 8K 8K
3.3V 3.3V 3.3V
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